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1 Ergebnisse
1
A Low-Latency and High-Performance SCL Decoder with Frame-I..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Zhang, Leyu
;
Ren, Yuqing
;
Shen, Yifei
... - p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10558152
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>A Low-Latency and High-Performance SCL Decoder with Frame-Interleaving</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10558152&Exemplar=1&LAN=DE A1 Zhang, Leyu A1 Ren, Yuqing A1 Shen, Yifei A1 Zhou, Wuyang A1 Balatsoukas-Stimming, Alexios A1 Zhang, Chuan A1 Burg, Andreas YR 2024 SN 2158-1525 K1 Codes K1 Circuits and systems K1 Computer architecture K1 Throughput K1 Hardware K1 Decoding K1 Computational efficiency K1 Polar codes K1 successive cancellation list (SCL) decoding K1 frame-interleaving K1 sequence repetition (SR) node K1 hardware architecture SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10558152 DO https://doi.org/10.1109/ISCAS58744.2024.10558152 SF ELIB - SuUB Bremen
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