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1 Ergebnisse
1
CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Guo, Yan-Cheng
;
Chang, Tian-Sheuan
;
Lin, Chih-Sheng
... - p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10558177
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10558177&Exemplar=1&LAN=DE A1 Guo, Yan-Cheng A1 Chang, Tian-Sheuan A1 Lin, Chih-Sheng A1 Chiou, Bo-Cheng A1 Lai, Chih-Ming A1 Sheu, Shyh-Shyuan A1 Lo, Wei-Chung A1 Chang, Shih-Chieh YR 2024 SN 2158-1525 K1 Semiconductor device modeling K1 Computational modeling K1 Pipelines K1 Full stack K1 Random access memory K1 Parallel processing K1 In-memory computing K1 Computing-in-memory K1 AI accelerator K1 Pruning framework SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10558177 DO https://doi.org/10.1109/ISCAS58744.2024.10558177 SF ELIB - SuUB Bremen
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