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1 Ergebnisse
1
Hybrid Multi-tile Vector Systolic Architecture for Accelera..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Shah, Jay
;
Rao, Nanditha
- p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10558268
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>Hybrid Multi-tile Vector Systolic Architecture for Accelerating Convolution on FPGAs</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10558268&Exemplar=1&LAN=DE A1 Shah, Jay A1 Rao, Nanditha YR 2024 SN 2158-1525 K1 Convolution K1 Circuits and systems K1 Computer architecture K1 Throughput K1 Vectors K1 Systolic arrays K1 Hardware K1 hardware accelerator K1 vector systolic accelerator K1 hybrid tile K1 FPGA SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10558268 DO https://doi.org/10.1109/ISCAS58744.2024.10558268 SF ELIB - SuUB Bremen
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