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1 Ergebnisse
1
Two-Step Spike Encoding Scheme and Architecture for Highly ..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Kim, Sangyeob
;
Kim, Sangjin
;
Um, Soyeon
.. - p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10558301
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>Two-Step Spike Encoding Scheme and Architecture for Highly Sparse Spiking-Neural-Network</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10558301&Exemplar=1&LAN=DE A1 Kim, Sangyeob A1 Kim, Sangjin A1 Um, Soyeon A1 Kim, Soyeon A1 Yoo, Hoi-Jun YR 2024 SN 2158-1525 K1 Maximum likelihood estimation K1 Accuracy K1 Throughput K1 Encoding K1 Hardware K1 Generators K1 Energy efficiency K1 Spiking-Neural-Network (SNN) K1 Rate Encoding K1 SNN Accelerator K1 Sparsity SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10558301 DO https://doi.org/10.1109/ISCAS58744.2024.10558301 SF ELIB - SuUB Bremen
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