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1 Ergebnisse
1
Low DRAM Memory Access and Flexible Dataflow Convolutional ..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Chen, Yi-Fan
;
Chang, Yu-Jen
;
Chiu, Ching-Te
... - p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10558316
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>Low DRAM Memory Access and Flexible Dataflow Convolutional Neural Network Accelerator based on RISC-V Custom Instruction</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10558316&Exemplar=1&LAN=DE A1 Chen, Yi-Fan A1 Chang, Yu-Jen A1 Chiu, Ching-Te A1 Huang, Ming-Long A1 Liang, Geng-Ming A1 Lee, Chao-Lin A1 Lee, Jenq-Kuen A1 Hsieh, Ping-Yu A1 Lai, Wei-Chih YR 2024 SN 2158-1525 K1 Circuits and systems K1 Computational modeling K1 Random access memory K1 Throughput K1 Space exploration K1 Convolutional neural networks K1 Computational complexity K1 Deep Convolutional Neural Network K1 Hardware Accelerator K1 Flexible Dataflow K1 High Utilization SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10558316 DO https://doi.org/10.1109/ISCAS58744.2024.10558316 SF ELIB - SuUB Bremen
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