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1 Ergebnisse
1
A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integ..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Wang, Zhongkai
;
Choi, Minsoo
;
Kwon, Paul
... - p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10558449
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>A 24.6-29.6GHz Hybrid Sub-Sampling PLL with Tri-State Integral Path Achieving 44fs Jitter and -254.8dB FOM in 28nm CMOS</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10558449&Exemplar=1&LAN=DE A1 Wang, Zhongkai A1 Choi, Minsoo A1 Kwon, Paul A1 Liu, Zhaokai A1 Yin, Bozhi A1 Lee, Kyoungtae A1 Park, Kwanseo A1 Biswas, Ayan A1 Han, Jaeduk A1 Du, Sijun A1 Alon, Elad YR 2024 SN 2158-1525 K1 Phase noise K1 Circuits and systems K1 Jitter K1 Delta-sigma modulation K1 Hybrid power systems K1 Phase locked loops K1 PLL K1 sub-sampling K1 hybrid K1 jitter K1 phase noise K1 28nm K1 CMOS SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10558449 DO https://doi.org/10.1109/ISCAS58744.2024.10558449 SF ELIB - SuUB Bremen
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