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1 Ergebnisse
1
A Two-step Fine-tuning Assisted Layout Sizing Scheme for An..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Wang, Zhikai
;
Ye, Zuochang
;
Zhou, Jingbo
.. - p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10558541
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>A Two-step Fine-tuning Assisted Layout Sizing Scheme for Analog/RF Circuits</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10558541&Exemplar=1&LAN=DE A1 Wang, Zhikai A1 Ye, Zuochang A1 Zhou, Jingbo A1 Liu, Xiaosen A1 Wang, Yan YR 2024 SN 2158-1525 K1 Technological innovation K1 Machine learning algorithms K1 Costs K1 Layout K1 Circuits K1 Transfer learning K1 Optimization K1 analog/RF circuits K1 layout sizing K1 fine-tuning assisted layout sizing (FALS) scheme SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10558541 DO https://doi.org/10.1109/ISCAS58744.2024.10558541 SF ELIB - SuUB Bremen
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