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1 Ergebnisse
1
3D Partitioning with Pipeline Optimization for Low-Latency ..:
, In:
2024 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Das, Sudipta
;
Riedel, Samuel
;
Bertuletti, Marco
... - p. 1-5 , 2024
Link:
https://doi.org/10.1109/ISCAS58744.2024.10558687
RT T1 <cTitle>2024 IEEE International Symposium on Circuits and Systems (ISCAS)</cTitle>: T1 <Title>3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10558687&Exemplar=1&LAN=DE A1 Das, Sudipta A1 Riedel, Samuel A1 Bertuletti, Marco A1 Benini, Luca A1 Brunion, Moritz A1 Ryckaert, Julien A1 Myers, James A1 Biswas, Dwaipayan A1 Milojevic, Dragomir YR 2024 SN 2158-1525 K1 Three-dimensional displays K1 Pipelines K1 Stacking K1 Integrated circuit interconnections K1 Computer architecture K1 System integration K1 System-on-chip K1 STCO K1 3D-IC K1 system architecture K1 interconnect architecture K1 3D partitioning K1 logic-on-logic K1 memory-on-logic SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS58744.2024.10558687 DO https://doi.org/10.1109/ISCAS58744.2024.10558687 SF ELIB - SuUB Bremen
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