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Analyzing the Low Power Techniques in SRAM Cells at 45nm No..:
, In:
2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
,
Dhariwal, Sandeep
;
Thomas, Aby K
;
Korah, Reeba
. - p. 1-5 , 2024
Link:
https://doi.org/10.1109/VLSISATA61709.2024.10560082
RT T1
2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
: T1
Analyzing the Low Power Techniques in SRAM Cells at 45nm Node Technology
UL https://suche.suub.uni-bremen.de/peid=ieee-10560082&Exemplar=1&LAN=DE A1 Dhariwal, Sandeep A1 Thomas, Aby K A1 Korah, Reeba A1 S, Manasi YR 2024 K1 Noise K1 Systems architecture K1 Logic gates K1 Very large scale integration K1 SRAM cells K1 CMOS technology K1 Delays K1 SRAM K1 Power dissipation K1 Low power techniques K1 Gated Vdd K1 MTCMOS K1 SoC SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/VLSISATA61709.2024.10560082 DO https://doi.org/10.1109/VLSISATA61709.2024.10560082 SF ELIB - SuUB Bremen
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