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1 Ergebnisse
1
Circuit Techniques for High Performance in CDDK Domino Logi:
, In:
2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)
,
Arun, V
;
Kumar, Himanshu
;
P, H Sasipriya
. - p. 1-4 , 2024
Link:
https://doi.org/10.1109/VLSISATA61709.2024.10560305
RT T1 <cTitle>2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)</cTitle>: T1 <Title>Circuit Techniques for High Performance in CDDK Domino Logic</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10560305&Exemplar=1&LAN=DE A1 Arun, V A1 Kumar, Himanshu A1 P, H Sasipriya A1 A, Anita Angeline YR 2024 K1 Technological innovation K1 Power demand K1 Logic gates K1 Very large scale integration K1 Discharges (electric) K1 Robustness K1 Delays K1 Pull-Down Network K1 Domino logic circuit K1 high fan-in K1 NMOS K1 PMOS K1 CMOS K1 Leakage power K1 Clock Delayed Dual Keeper circuits SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/VLSISATA61709.2024.10560305 DO https://doi.org/10.1109/VLSISATA61709.2024.10560305 SF ELIB - SuUB Bremen
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