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A Low Voltage 6T SRAM Cell Design and Analysis Using Cadenc..:
, In:
2024 7th International Conference on Devices, Circuits and Systems (ICDCS)
,
Kalpana, T.
;
Reddy, Challa Lakshmi
;
Saranya, Bandaru
. - p. 188-194 , 2024
Link:
https://doi.org/10.1109/ICDCS59278.2024.10560497
RT T1 <cTitle>2024 7th International Conference on Devices, Circuits and Systems (ICDCS)</cTitle>: T1 <Title>A Low Voltage 6T SRAM Cell Design and Analysis Using Cadence 90nm And 45nm CMOS Technology</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10560497&Exemplar=1&LAN=DE A1 Kalpana, T. A1 Reddy, Challa Lakshmi A1 Saranya, Bandaru A1 Naveen, Poluboyina YR 2024 SN 2644-1802 K1 Power demand K1 Simulation K1 Layout K1 Very large scale integration K1 SRAM cells K1 Delays K1 Transistors K1 6T SRAM cell K1 CMOS technology K1 Cadence tool K1 Power consumption K1 High-speed applications SP 188 OP 194 LK http://dx.doi.org/https://doi.org/10.1109/ICDCS59278.2024.10560497 DO https://doi.org/10.1109/ICDCS59278.2024.10560497 SF ELIB - SuUB Bremen
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