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1 Ergebnisse
1
Design of Shift Registers Using DG-FinFET for Low Power App..:
, In:
2024 7th International Conference on Devices, Circuits and Systems (ICDCS)
,
Shanthi, G.
;
Naga Vaishnavi, K.
;
Manasa, N.
... - p. 151-155 , 2024
Link:
https://doi.org/10.1109/ICDCS59278.2024.10560604
RT T1 <cTitle>2024 7th International Conference on Devices, Circuits and Systems (ICDCS)</cTitle>: T1 <Title>Design of Shift Registers Using DG-FinFET for Low Power Applications</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10560604&Exemplar=1&LAN=DE A1 Shanthi, G. A1 Naga Vaishnavi, K. A1 Manasa, N. A1 Surya Pramod, V. A1 Naga Leela, S. A1 Shoukath Vali, Shaik YR 2024 SN 2644-1802 K1 Performance evaluation K1 Power demand K1 Delay effects K1 Noise K1 FinFETs K1 Shift registers K1 Circuit synthesis K1 FinFET K1 Shift Register K1 Power dissipation K1 Time delay K1 Serial In-Parallel Out (SIPO) K1 Serial in-Serial Out (SISO) K1 Parallel In-Parallel Out (PIPO) K1 Parallel In-Serial Out (PISO) SP 151 OP 155 LK http://dx.doi.org/https://doi.org/10.1109/ICDCS59278.2024.10560604 DO https://doi.org/10.1109/ICDCS59278.2024.10560604 SF ELIB - SuUB Bremen
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