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Power Efficiency Evaluation of Dual Edge Triggered Flip-Flo..:
, In:
2024 7th International Conference on Devices, Circuits and Systems (ICDCS)
,
Murugesan, Parthiban
;
Rajeev, Sreenidhi Prabha
- p. 112-116 , 2024
Link:
https://doi.org/10.1109/ICDCS59278.2024.10560917
RT T1 <cTitle>2024 7th International Conference on Devices, Circuits and Systems (ICDCS)</cTitle>: T1 <Title>Power Efficiency Evaluation of Dual Edge Triggered Flip-Flops - A Comparative Analysis</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10560917&Exemplar=1&LAN=DE A1 Murugesan, Parthiban A1 Rajeev, Sreenidhi Prabha YR 2024 SN 2644-1802 K1 Performance evaluation K1 Power demand K1 Circuits and systems K1 Throughput K1 Sequential circuits K1 Transistors K1 Integrated circuit modeling K1 Dual Edge Triggered Flip Flop (DET FF) K1 45nm K1 C-Element K1 Clocked DET K1 Latch-MUX K1 Contention free K1 Fully Static K1 Spectre K1 Virtuoso SP 112 OP 116 LK http://dx.doi.org/https://doi.org/10.1109/ICDCS59278.2024.10560917 DO https://doi.org/10.1109/ICDCS59278.2024.10560917 SF ELIB - SuUB Bremen
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