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1
A Novel Design of Area Efficient Full Adder Architecture Us..:
, In:
2024 7th International Conference on Devices, Circuits and Systems (ICDCS)
,
Ganesh, Chokkakula
;
Kumar, Aruru Sai
;
Santhosh, P
... - p. 107-111 , 2024
Link:
https://doi.org/10.1109/ICDCS59278.2024.10560999
RT T1 <cTitle>2024 7th International Conference on Devices, Circuits and Systems (ICDCS)</cTitle>: T1 <Title>A Novel Design of Area Efficient Full Adder Architecture Using Reversible Logic Gates</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10560999&Exemplar=1&LAN=DE A1 Ganesh, Chokkakula A1 Kumar, Aruru Sai A1 Santhosh, P A1 Ramya, Anreddy A1 Kumar, Chennoji Shiva A1 Thivani, Ponugoti YR 2024 SN 2644-1802 K1 Reversible computing K1 Quantum computing K1 Costs K1 Circuits and systems K1 Computer architecture K1 Logic gates K1 Software K1 Quantum Computing K1 Ancillae K1 Quantum Cost K1 Reversible gates and Low-Power SP 107 OP 111 LK http://dx.doi.org/https://doi.org/10.1109/ICDCS59278.2024.10560999 DO https://doi.org/10.1109/ICDCS59278.2024.10560999 SF ELIB - SuUB Bremen
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