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1 Ergebnisse
1
Design and Analysis of 4 Bit Multipliers Using Pass Transis..:
, In:
2024 7th International Conference on Devices, Circuits and Systems (ICDCS)
,
P, Pavithara
;
M, Ramesh
;
M, Prabu
... - p. 291-295 , 2024
Link:
https://doi.org/10.1109/ICDCS59278.2024.10561038
RT T1 <cTitle>2024 7th International Conference on Devices, Circuits and Systems (ICDCS)</cTitle>: T1 <Title>Design and Analysis of 4 Bit Multipliers Using Pass Transistor Logic and Gate Diffusion Input Technique Using 18nm FinFET Technology</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10561038&Exemplar=1&LAN=DE A1 P, Pavithara A1 M, Ramesh A1 M, Prabu A1 K, Kavin Kumar A1 P, Ponmurugan A1 V, Udaya Suriyan YR 2024 SN 2644-1802 K1 Power demand K1 Filtering K1 Digital signal processing K1 Logic gates K1 FinFETs K1 Delays K1 Logic K1 FinFET K1 PTL K1 GDI K1 Array Multiplier K1 Wallace tree multiplier K1 Power K1 Delay SP 291 OP 295 LK http://dx.doi.org/https://doi.org/10.1109/ICDCS59278.2024.10561038 DO https://doi.org/10.1109/ICDCS59278.2024.10561038 SF ELIB - SuUB Bremen
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