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1 Ergebnisse
1
Room-Temperature Hybrid Bonding of Via-middle TSV Wafer Fab..:
, In:
2024 IEEE 74th Electronic Components and Technology Conference (ECTC)
,
Watanabe, Naoya
;
Yamamoto, Hiroshi
;
Mitsui, Takahiko
- p. 2101-2106 , 2024
Link:
https://doi.org/10.1109/ECTC51529.2024.00358
RT T1 <cTitle>2024 IEEE 74th Electronic Components and Technology Conference (ECTC)</cTitle>: T1 <Title>Room-Temperature Hybrid Bonding of Via-middle TSV Wafer Fabricated by Direct Si/Cu Grinding and Residual Metal Removal</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10565051&Exemplar=1&LAN=DE A1 Watanabe, Naoya A1 Yamamoto, Hiroshi A1 Mitsui, Takahiko YR 2024 SN 2377-5726 K1 Resistance K1 Electrodes K1 Annealing K1 Stacking K1 Metals K1 Glass K1 Silicon K1 three-dimensional integrated circuits (3D-ICs) K1 via-middle K1 through-silicon via (TSV) K1 direct Si/Cu grinding K1 residual metal removal treatment K1 hybrid bonding SP 2101 OP 2106 LK http://dx.doi.org/https://doi.org/10.1109/ECTC51529.2024.00358 DO https://doi.org/10.1109/ECTC51529.2024.00358 SF ELIB - SuUB Bremen
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