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1 Ergebnisse
1
Multi-Chip Stacked Memory Module Development using Chip to ..:
, In:
2024 IEEE 74th Electronic Components and Technology Conference (ECTC)
,
Sekhar, Vasarla Nagendra
;
Kumar, Mishra Dileep
;
Tippabhotla, Sasi Kumar
... - p. 2024-2030 , 2024
Link:
https://doi.org/10.1109/ECTC51529.2024.00345
RT T1 <cTitle>2024 IEEE 74th Electronic Components and Technology Conference (ECTC)</cTitle>: T1 <Title>Multi-Chip Stacked Memory Module Development using Chip to Wafer (C2W) Hybrid Bonding for Heterogeneous Integration Applications</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10565135&Exemplar=1&LAN=DE A1 Sekhar, Vasarla Nagendra A1 Kumar, Mishra Dileep A1 Tippabhotla, Sasi Kumar A1 Rao, B. S. S. Chandra A1 Daniel, Ismael Cereno A1 Chong, Ser Choong A1 Rao, Vempati Srinivasa YR 2024 SN 2377-5726 K1 Fabrication K1 Semiconductor device modeling K1 Stacking K1 Dielectric materials K1 Memory modules K1 Dielectrics K1 Finite element analysis K1 chip-to-wafer hybrid bonding K1 multi-chip stacking K1 finite element analysis K1 thin wafer handling K1 process challenges K1 and mitigation plans SP 2024 OP 2030 LK http://dx.doi.org/https://doi.org/10.1109/ECTC51529.2024.00345 DO https://doi.org/10.1109/ECTC51529.2024.00345 SF ELIB - SuUB Bremen
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