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Key Technologies and Design Aspects for Wafer Level Packagi..:
, In:
2024 IEEE 74th Electronic Components and Technology Conference (ECTC)
,
Zoschke, Kai
;
Oppermann, Hermann
;
Schiffer, Michael
... - p. 433-440 , 2024
Link:
https://doi.org/10.1109/ECTC51529.2024.00340
RT T1 <cTitle>2024 IEEE 74th Electronic Components and Technology Conference (ECTC)</cTitle>: T1 <Title>Key Technologies and Design Aspects for Wafer Level Packaging of High Performance Computing Modules</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10565181&Exemplar=1&LAN=DE A1 Zoschke, Kai A1 Oppermann, Hermann A1 Schiffer, Michael A1 Ndip, Ivan A1 Becker, Karl-Friedrich A1 Adler, Marius A1 Gabler, Alexander A1 Maas, Uwe A1 Paulin, Gianna A1 Kocon, Walter YR 2024 SN 2377-5726 K1 High performance computing K1 Packaging K1 Routing K1 Silicon K1 Wafer scale integration K1 Laser ablation K1 Copper K1 high performance computing K1 wafer level packaging K1 high density redistribution K1 silicon interposer K1 through silicon vias (TSVs) K1 chiplet SP 433 OP 440 LK http://dx.doi.org/https://doi.org/10.1109/ECTC51529.2024.00340 DO https://doi.org/10.1109/ECTC51529.2024.00340 SF ELIB - SuUB Bremen
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