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1 Ergebnisse
1
Optimizing Logical Execution Time Model for Both Determinis..:
, In:
2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)
,
Wang, Sen
;
Li, Dong
;
Sifat, Ashrarul H.
... - p. 135-148 , 2024
Link:
https://doi.org/10.1109/RTAS61025.2024.00019
RT T1 <cTitle>2024 IEEE 30th Real-Time and Embedded Technology and Applications Symposium (RTAS)</cTitle>: T1 <Title>Optimizing Logical Execution Time Model for Both Determinism and Low Latency</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10568041&Exemplar=1&LAN=DE A1 Wang, Sen A1 Li, Dong A1 Sifat, Ashrarul H. A1 Huang, Shao-Yu A1 Deng, Xuanliang A1 Jung, Changhee A1 Williams, Ryan A1 Zeng, Haibo YR 2024 SN 2642-7346 K1 Measurement K1 Protocols K1 Jitter K1 Programming K1 Real-time systems K1 Timing K1 Space exploration K1 Real-Time Systems K1 Logical Execution Time K1 Optimization K1 End-to-end latency K1 latency K1 time disparity K1 Determinism K1 symbolic optimization K1 communication protocol K1 cause-effect chain K1 DAG K1 reaction time K1 data age K1 LET SP 135 OP 148 LK http://dx.doi.org/https://doi.org/10.1109/RTAS61025.2024.00019 DO https://doi.org/10.1109/RTAS61025.2024.00019 SF ELIB - SuUB Bremen
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