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1 Ergebnisse
1
Design of VLSI Architecture Using AES Algorithm:
, In:
2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT)
,
Indra, J
;
Shiny Pershiya, A
- p. 1-6 , 2024
Link:
https://doi.org/10.1109/AIIoT58432.2024.10574781
RT T1
2024 3rd International Conference on Artificial Intelligence For Internet of Things (AIIoT)
: T1
Design of VLSI Architecture Using AES Algorithm
UL https://suche.suub.uni-bremen.de/peid=ieee-10574781&Exemplar=1&LAN=DE A1 Indra, J A1 Shiny Pershiya, A YR 2024 K1 Performance evaluation K1 Signal processing algorithms K1 Very large scale integration K1 Parallel processing K1 Data processing K1 Throughput K1 Real-time systems K1 VLSI Architecture K1 Discrete Wavelet Transform K1 Advanced Encryption Standard K1 Signal processing SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/AIIoT58432.2024.10574781 DO https://doi.org/10.1109/AIIoT58432.2024.10574781 SF ELIB - SuUB Bremen
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