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1 Ergebnisse
1
Closed-Loop Structure for Mitigating Jitter-Induced Noise o..:
, In:
2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa)
,
Wu, Haojie
;
Meng, Xiangyu
;
Bao, Qidong
... - p. 194-197 , 2024
Link:
https://doi.org/10.23919/EMCJapan/APEMCOkinaw58965.202..
RT T1 <cTitle>2024 IEEE Joint International Symposium on Electromagnetic Compatibility, Signal & Power Integrity: EMC Japan / Asia-Pacific International Symposium on Electromagnetic Compatibility (EMC Japan/APEMC Okinawa)</cTitle>: T1 <Title>Closed-Loop Structure for Mitigating Jitter-Induced Noise of Clock Source in High-Bandwidth Signal Sampling</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10585015&Exemplar=1&LAN=DE A1 Wu, Haojie A1 Meng, Xiangyu A1 Bao, Qidong A1 Wang, Wenrui A1 Sun, Yin A1 Sun, Xinglin YR 2024 SN 2640-7469 K1 Phase noise K1 Couplings K1 System performance K1 Simulation K1 Signal sampling K1 Jitter K1 Electromagnetic compatibility K1 High-bandwidth sampling K1 analog-to-digital converter K1 clock jitter K1 jitter-induced noise K1 closed-loop SP 194 OP 197 LK http://dx.doi.org/https://doi.org/10.23919/EMCJapan/APEMCOkinaw58965.2024.10585015 DO https://doi.org/10.23919/EMCJapan/APEMCOkinaw58965.2024.10585015 SF ELIB - SuUB Bremen
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