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1
FlattenRTL: An Open Source Tool for Flattening Verilog Modu..:
, In:
2024 2nd International Symposium of Electronics Design Automation (ISEDA)
,
Meng, Xiangchen
;
Zheng, Ziyue
;
Lyu, Yangdi
- p. 752-757 , 2024
Link:
https://doi.org/10.1109/ISEDA62518.2024.10617584
RT T1 <cTitle>2024 2nd International Symposium of Electronics Design Automation (ISEDA)</cTitle>: T1 <Title>FlattenRTL: An Open Source Tool for Flattening Verilog Module at RTL Level</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10617584&Exemplar=1&LAN=DE A1 Meng, Xiangchen A1 Zheng, Ziyue A1 Lyu, Yangdi YR 2024 K1 Design automation K1 Codes K1 Memory management K1 Benchmark testing K1 Syntactics K1 Hardware K1 Complexity theory K1 Verilog K1 RTL K1 Flatten SP 752 OP 757 LK http://dx.doi.org/https://doi.org/10.1109/ISEDA62518.2024.10617584 DO https://doi.org/10.1109/ISEDA62518.2024.10617584 SF ELIB - SuUB Bremen
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