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1
Efficient Verification Framework for RISC-V Instruction Ext..:
, In:
2024 2nd International Symposium of Electronics Design Automation (ISEDA)
,
Jiang, Zijian
;
Zheng, Keran
;
Bao, Yungang
. - p. 345-350 , 2024
Link:
https://doi.org/10.1109/ISEDA62518.2024.10618013
RT T1 <cTitle>2024 2nd International Symposium of Electronics Design Automation (ISEDA)</cTitle>: T1 <Title>Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10618013&Exemplar=1&LAN=DE A1 Jiang, Zijian A1 Zheng, Keran A1 Bao, Yungang A1 Shi, Kan YR 2024 K1 Instruction sets K1 Integrated circuit interconnections K1 Computer architecture K1 Software K1 Real-time systems K1 Distance measurement K1 High level languages K1 Verification K1 RISC-V instruction extension K1 FPGA acceleration K1 High-level synthesis SP 345 OP 350 LK http://dx.doi.org/https://doi.org/10.1109/ISEDA62518.2024.10618013 DO https://doi.org/10.1109/ISEDA62518.2024.10618013 SF ELIB - SuUB Bremen
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