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1 Ergebnisse
1
MDCRA: A Reconfigurable Accelerator Framework for Multiple ..:
, In:
2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
,
Sun, Shaoyang
;
Jin, Boyin
;
Lou, Jiahang
... - p. 133-134 , 2024
Link:
https://doi.org/10.1109/ASAP61560.2024.00036
RT T1 <cTitle>2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)</cTitle>: T1 <Title>MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10631152&Exemplar=1&LAN=DE A1 Sun, Shaoyang A1 Jin, Boyin A1 Lou, Jiahang A1 Li, Jiangnan A1 Cao, Yuhang A1 Li, Jingyuan A1 Shen, Chen A1 Dai, Yuan A1 Yin, Wenbo A1 Luk, Wai-Shing A1 Wang, Lingli YR 2024 SN 2160-052X K1 Program processors K1 Systems architecture K1 Hardware K1 Reconfigurable architectures K1 Vector processors K1 Resource management K1 Dynamic compiler SP 133 OP 134 LK http://dx.doi.org/https://doi.org/10.1109/ASAP61560.2024.00036 DO https://doi.org/10.1109/ASAP61560.2024.00036 SF ELIB - SuUB Bremen
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