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1 Ergebnisse
1
A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM w..:
, In:
2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
,
Tanaka, Tomotaka
;
Ishii, Yuichiro
;
Yabuuchi, Makoto
... - p. 1-2 , 2024
Link:
https://doi.org/10.1109/VLSITechnologyandCir46783.2024..
RT T1 <cTitle>2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)</cTitle>: T1 <Title>A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-10631525&Exemplar=1&LAN=DE A1 Tanaka, Tomotaka A1 Ishii, Yuichiro A1 Yabuuchi, Makoto A1 Aoyagi, Yumito A1 Hamada, Masaya A1 Mizutani, Kazuto A1 Nii, Koji A1 Fujiwara, Hidehiro A1 Wang, Isabel A1 Cheng, Hong-Chen A1 Liao, Hung-Jen A1 Chang, Tsung-Yung Jonathan YR 2024 SN 2158-9682 K1 Random access memory K1 Very large scale integration K1 Wire K1 3nm K1 PDP K1 2RW K1 SRAM K1 dynamic power K1 bit-density SP 1 OP 2 LK http://dx.doi.org/https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631525 DO https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631525 SF ELIB - SuUB Bremen
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