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1
Modeling for computation of IC-gate yield from processing d..:
, In:
1972 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
,
Wilson, C.
;
Dowell, R.
- p. 68,69 , 1972
Link:
https://doi.org/10.1109/ISSCC.1972.1155094
RT T1
1972 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
: T1
Modeling for computation of IC-gate yield from processing data
UL https://suche.suub.uni-bremen.de/peid=ieee-1155094&Exemplar=1&LAN=DE A1 Wilson, C. A1 Dowell, R. YR 1972 K1 Computational modeling K1 Voltage K1 Circuit analysis K1 Impurities K1 Circuit analysis computing K1 Conductivity K1 Semiconductor process modeling K1 Doping K1 Solid state circuits K1 Gain measurement SP 68,69 LK http://dx.doi.org/https://doi.org/10.1109/ISSCC.1972.1155094 DO https://doi.org/10.1109/ISSCC.1972.1155094 SF ELIB - SuUB Bremen
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