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1 Ergebnisse
1
Low temperature CMOS 8 × 8b multipliers with sub 10ns speed:
, In:
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
,
Hanamura, S.
;
Aoki, M.
;
Masuhara, T.
... - p. 210,211 , 1985
Link:
https://doi.org/10.1109/ISSCC.1985.1156789
RT T1
1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
: T1
Low temperature CMOS 8 × 8b multipliers with sub 10ns speeds
UL https://suche.suub.uni-bremen.de/peid=ieee-1156789&Exemplar=1&LAN=DE A1 Hanamura, S. A1 Aoki, M. A1 Masuhara, T. A1 Minato, O. A1 Sakai, Y. A1 Hayashida, T. YR 1985 K1 Temperature K1 Gallium arsenide K1 Power dissipation K1 Helium K1 Delay K1 Very large scale integration K1 Circuits K1 Nitrogen K1 Inverters K1 CMOS technology SP 210,211 LK http://dx.doi.org/https://doi.org/10.1109/ISSCC.1985.1156789 DO https://doi.org/10.1109/ISSCC.1985.1156789 SF ELIB - SuUB Bremen
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