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A 47ns 64KW × 4b CMOS DRAM with relaxed timing requirements:

, In: 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers,
Kobayashi, T. ; Arimoto, K. ; Ikeda, Y.... - p. 260,261 , 1986
Link: https://doi.org/10.1109/ISSCC.1986.1156944