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Gate stack optimization for 65 nm CMOS low power and high p..:

, In: IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.,
Duriez, B. ; Tavel, B. ; Boeuf, R.... - p. 847,848,849,850 , 2004
Link: https://doi.org/10.1109/IEDM.2004.1419311