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1 Ergebnisse
1
Congestion and performance driven full-chip scalable routin..:
, In:
2005 6th International Conference on ASIC
,
Hailong Yao
;
Yici Cai
;
Xianlong Hong
. - p. 856-859 , 2005
Link:
https://doi.org/10.1109/ICASIC.2005.1611440
RT T1
2005 6th International Conference on ASIC
: T1
Congestion and performance driven full-chip scalable routing framework
UL https://suche.suub.uni-bremen.de/peid=ieee-1611440&Exemplar=1&LAN=DE A1 Hailong Yao A1 Yici Cai A1 Xianlong Hong A1 Qiang Zhou YR 2005 SN 2162-7541 SN 2162-755X K1 Routing K1 Timing K1 Circuit optimization K1 Circuit testing K1 Very large scale integration K1 Electronic design automation and methodology K1 Benchmark testing K1 Clocks K1 Frequency K1 Integrated circuit interconnections SP 856 OP 859 LK http://dx.doi.org/https://doi.org/10.1109/ICASIC.2005.1611440 DO https://doi.org/10.1109/ICASIC.2005.1611440 SF ELIB - SuUB Bremen
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