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1 Ergebnisse
1
A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniq..:
, In:
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers
,
Brox, M.
;
Schmolz, P.
;
Schrogmeier, P.
... - p. 537-546 , 2006
Link:
https://doi.org/10.1109/ISSCC.2006.1696090
RT T1
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers
: T1
A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques
UL https://suche.suub.uni-bremen.de/peid=ieee-1696090&Exemplar=1&LAN=DE A1 Brox, M. A1 Schmolz, P. A1 Schrogmeier, P. A1 Tuber, A. A1 Weber, B. A1 Mayer, P. A1 Spirkl, W. A1 Steffens, H. A1 Weller, J. A1 Fibranz, H. A1 Kuzmenka, M. A1 Lu, F. A1 Mann, S. A1 Markert, M. A1 Moller, U. A1 Plan, M. A1 Schiller, K. YR 2006 SN 0193-6530 SN 2376-8606 K1 Graphics K1 Random access memory K1 Voltage K1 Parasitic capacitance K1 Resonance K1 Propagation delay K1 MOS devices K1 Acceleration K1 Bandwidth K1 Jitter SP 537 OP 546 LK http://dx.doi.org/https://doi.org/10.1109/ISSCC.2006.1696090 DO https://doi.org/10.1109/ISSCC.2006.1696090 SF ELIB - SuUB Bremen
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