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Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm ..:

, In: 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.,

Park, Sung-Wook ; Hong, Sung-Joo ; Kim, Jin-Woong... - p. 32-33 , 2006

Link: https://doi.org/10.1109/VLSIT.2006.1705202

RT 
T1 <cTitle>2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.</cTitle>: T1 <Title>Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-1705202&Exemplar=1&LAN=DE
				
A1 Park, Sung-Wook
A1 Hong, Sung-Joo
A1 Kim, Jin-Woong
A1 Jeong, Jae-Goan
A1 Yoo, Kyung-Dong
A1 Moon, Seung-Chan
A1 Sohn, Hyun-Chul
A1 Kwak, Noh-Jung
A1 Cho, Yun-Seok
A1 Baek, Seung-Joo
A1 Park, Hyung-Soon
A1 Yoon, Hyo Geun
A1 Lee, Bong-Hoon
A1 Kim, Jin-Soo
A1 Hwang, Sun-Hwan
A1 Lee, Lae-Hee
A1 Cho, Heung-Jae
A1 Cho, Sung Yoon
A1 Chung, Chai-O
A1 Kim, Kwang-Ok
A1 Yoo, Min-Soo
A1 Jang, Se-Aug
A1 Lee, Sang-Don
A1 Chung, Sung-Woong
YR 2006
SN 0743-1562
SN 2158-9682
K1 Random access memory
K1 FinFETs
K1 Etching
K1 Silicon
K1 Threshold voltage
K1 Doping
K1 Controllability
K1 Transconductance
K1 Moon
K1 Research and development
SP 32
OP 33
LK http://dx.doi.org/https://doi.org/10.1109/VLSIT.2006.1705202
DO https://doi.org/10.1109/VLSIT.2006.1705202
SF ELIB - SuUB Bremen

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