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Strain-Enhanced CMOS Through Novel Process-Substrate Stress..:

, In: 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.,

Mazure, C. ; Cayrefourcq, I. ; Mogab, J.... - p. 130-131 , 2006

Link: https://doi.org/10.1109/VLSIT.2006.1705251

RT 
T1 <cTitle>2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.</cTitle>: T1 <Title>Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-1705251&Exemplar=1&LAN=DE
				
A1 Mazure, C.
A1 Cayrefourcq, I.
A1 Mogab, J.
A1 Venkatesan, S.
A1 White, B.E.
A1 Nguyen, B.-Y.
A1 White, T.
A1 Burnett, D.
A1 La, L.-B.
A1 Backer, S.
A1 Prabhu, L.
A1 Dhandapani, V.
A1 Goolsby, B.
A1 Wang, X.-D.
A1 Goedeke, D.
A1 Filipiak, S.
A1 Spencer, G.
A1 Murphy, S.
A1 Shi, Z.-H.
A1 Gu, B.
A1 Grudowski, P.
A1 Desjardin, H.
A1 Canonico, M.
A1 Conner, J.
A1 Adams, V.
A1 Vartanian, V.
A1 Zhang, D.
A1 Thean, A.V.-Y.
YR 2006
SN 0743-1562
SN 2158-9682
K1 CMOS process
K1 Stress
K1 Insulation
K1 CMOS technology
K1 Silicon on insulator technology
K1 Silicon germanium
K1 Germanium silicon alloys
K1 Capacitive sensors
K1 Leakage current
K1 Scalability
SP 130
OP 131
LK http://dx.doi.org/https://doi.org/10.1109/VLSIT.2006.1705251
DO https://doi.org/10.1109/VLSIT.2006.1705251
SF ELIB - SuUB Bremen

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