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1
A Leakage Management System Based on Clock Gating Infrastru..:
, In:
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.
,
Ko, U.
;
Raibaut, C.
;
Ciroux, J.
... - p. 214-215 , 2006
Link:
https://doi.org/10.1109/VLSIC.2006.1705386
RT T1
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.
: T1
A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip
UL https://suche.suub.uni-bremen.de/peid=ieee-1705386&Exemplar=1&LAN=DE A1 Ko, U. A1 Raibaut, C. A1 Ciroux, J. A1 Fournet-Fayard, C. A1 Lachese, J.L. A1 Domerego, O. A1 Bouetel, L. A1 Ben-Amar, F. A1 Ball, M. A1 Rosal, J. A1 Culp, N. A1 Piacibello, F. A1 Vaccani, J. A1 Hollingsworth, R. A1 Menezes, V. A1 Clinton, M. A1 Thiruvengadam, S. A1 Gururajarao, S. A1 Chau, M. A1 Lagerquist, R. A1 Er Rachidi, A. A1 Scott, D. A1 Mair, H. A1 Royannez, P. A1 Jumel, F. YR 2006 SN 2158-5601 SN 2158-5636 K1 Clocks K1 Modems K1 Power system management K1 Energy management K1 Switches K1 Control systems K1 Random access memory K1 Voltage K1 Circuits K1 Leakage current SP 214 OP 215 LK http://dx.doi.org/https://doi.org/10.1109/VLSIC.2006.1705386 DO https://doi.org/10.1109/VLSIC.2006.1705386 SF ELIB - SuUB Bremen
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