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1 Ergebnisse
1
Merged-Cascaded Systolic Array for VLSI Implementation of D..:
, In:
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems
,
Meher, Pramod K.
- p. None , 2006
Link:
https://doi.org/10.1109/APCCAS.2006.342489
RT T1 <cTitle>APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems</cTitle>: T1 <Title>Merged-Cascaded Systolic Array for VLSI Implementation of Discrete Wavelet Transform</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-4145431&Exemplar=1&LAN=DE A1 Meher, Pramod K. YR 2006 K1 Discrete wavelet transforms K1 Systolic arrays K1 Very large scale integration K1 Computer architecture K1 Filters K1 Discrete Fourier transforms K1 High performance computing K1 Hardware K1 Algorithm design and analysis K1 Fourier transforms SP None LK http://dx.doi.org/https://doi.org/10.1109/APCCAS.2006.342489 DO https://doi.org/10.1109/APCCAS.2006.342489 SF ELIB - SuUB Bremen
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