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Three dimensional chip stacking using a wafer-to-wafer inte..:

, In: 2007 IEEE International Interconnect Technology Conferencee,

Chatterjee, Ritwik ; Zussy, Marc ; Roman, Antonio... - p. None , 2007

Link: https://doi.org/10.1109/IITC.2007.382355

RT 
T1 <cTitle>2007 IEEE International Interconnect Technology Conferencee</cTitle>: T1 <Title>Three dimensional chip stacking using a wafer-to-wafer integration</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-4263667&Exemplar=1&LAN=DE
				
A1 Chatterjee, Ritwik
A1 Zussy, Marc
A1 Roman, Antonio
A1 Louveau, Olivier
A1 Maitrejean, Sylvain
A1 Louis, Didier
A1 Kernevez, Nelly
A1 Sillon, Nicolas
A1 Passemard, Gerard
A1 Pol, Victor
A1 Mathew, Varughese
A1 Fayolle, Murielle
A1 Garcia, Sam
A1 Sparks, Terry
A1 Huang, Zhihong
A1 Leduc, Patrick
A1 Pozder, Scott
A1 Jones, Bob
A1 Acosta, Eddie
A1 Charlet, Barbara
A1 Enot, Thierry
A1 Heitzmann, Michel
YR 2007
SN 2380-632X
SN 2380-6338
K1 Stacking
K1 Wafer bonding
K1 Integrated circuit interconnections
K1 Integrated circuit technology
K1 Silicon on insulator technology
K1 Dielectric measurements
K1 Throughput
K1 Electric variables measurement
K1 Size measurement
K1 Testing
SP None
LK http://dx.doi.org/https://doi.org/10.1109/IITC.2007.382355
DO https://doi.org/10.1109/IITC.2007.382355
SF ELIB - SuUB Bremen

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