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1 Ergebnisse
1
LVDS-type on-chip transmision line interconnect with passiv..:
, In:
2008 Asia and South Pacific Design Automation Conference
,
Akiko Mineyama
;
Hiroyuki Ito
;
Takahiro Ishii
.. - p. None , 2008
Link:
https://doi.org/10.1109/ASPDAC.2008.4484069
RT T1
2008 Asia and South Pacific Design Automation Conference
: T1
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process
UL https://suche.suub.uni-bremen.de/peid=ieee-4484069&Exemplar=1&LAN=DE A1 Akiko Mineyama A1 Hiroyuki Ito A1 Takahiro Ishii A1 Kenichi Okada A1 Kazuya Masu YR 2008 SN 2153-6961 SN 2153-697X K1 Equalizers K1 CMOS process K1 Integrated circuit interconnections K1 Delay K1 Energy consumption K1 Frequency dependence K1 Inductors K1 Low voltage K1 Power transmission lines K1 Timing SP None LK http://dx.doi.org/https://doi.org/10.1109/ASPDAC.2008.4484069 DO https://doi.org/10.1109/ASPDAC.2008.4484069 SF ELIB - SuUB Bremen
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