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1 Ergebnisse
1
Structured LDPC codes with low error floor based on PEG tan..:
, In:
2008 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Yi-Kai Lin
;
Chih-Lung Chen
;
Yen-Chin Liao
. - p. None , 2008
Link:
https://doi.org/10.1109/ISCAS.2008.4541800
RT T1
2008 IEEE International Symposium on Circuits and Systems (ISCAS)
: T1
Structured LDPC codes with low error floor based on PEG tanner graphs
UL https://suche.suub.uni-bremen.de/peid=ieee-4541800&Exemplar=1&LAN=DE A1 Yi-Kai Lin A1 Chih-Lung Chen A1 Yen-Chin Liao A1 Hsie-Chia Chang YR 2008 SN 0271-4302 SN 2158-1525 K1 Parity check codes K1 Floors K1 Algorithm design and analysis K1 Very large scale integration K1 Bit error rate K1 Encoding K1 Error analysis K1 Block codes K1 Sparse matrices K1 Iterative decoding SP None LK http://dx.doi.org/https://doi.org/10.1109/ISCAS.2008.4541800 DO https://doi.org/10.1109/ISCAS.2008.4541800 SF ELIB - SuUB Bremen
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