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1 Ergebnisse
1
Anticipatory access pipeline design for phased cache:
, In:
2008 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Chih-Wen Hsueh
;
Jen-Feng Chung
;
Lan-Da Van
. - p. None , 2008
Link:
https://doi.org/10.1109/ISCAS.2008.4541924
RT T1
2008 IEEE International Symposium on Circuits and Systems (ISCAS)
: T1
Anticipatory access pipeline design for phased cache
UL https://suche.suub.uni-bremen.de/peid=ieee-4541924&Exemplar=1&LAN=DE A1 Chih-Wen Hsueh A1 Jen-Feng Chung A1 Lan-Da Van A1 Chin-Teng Lin YR 2008 SN 0271-4302 SN 2158-1525 K1 Energy consumption K1 Pipeline processing K1 Process design K1 Microprocessors K1 Control engineering K1 Computer science K1 Cache memory K1 Phase detection K1 Filters K1 Costs SP None LK http://dx.doi.org/https://doi.org/10.1109/ISCAS.2008.4541924 DO https://doi.org/10.1109/ISCAS.2008.4541924 SF ELIB - SuUB Bremen
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