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1 Ergebnisse
1
Validation of hardware error recovery mechanisms for the SP..:
, In:
2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)
,
Hisashige Ando
;
Ryuji Kan
;
Yoshiharu Tosaka
.. - p. None , 2008
Link:
https://doi.org/10.1109/DSN.2008.4630071
RT T1
2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)
: T1
Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor
UL https://suche.suub.uni-bremen.de/peid=ieee-4630071&Exemplar=1&LAN=DE A1 Hisashige Ando A1 Ryuji Kan A1 Yoshiharu Tosaka A1 Takahisa, Keiji A1 Kichiji Hatanaka YR 2008 SN 1530-0889 SN 2158-3927 SP None LK http://dx.doi.org/https://doi.org/10.1109/DSN.2008.4630071 DO https://doi.org/10.1109/DSN.2008.4630071 SF ELIB - SuUB Bremen
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