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1 Ergebnisse
1
CriAS: A performance-driven criticality-aware synthesis flo..:
, In:
2009 Asia and South Pacific Design Automation Conference
,
Chia-I Chen
;
Huang, Juinn-Dar
- p. None , 2009
Link:
https://doi.org/10.1109/ASPDAC.2009.4796443
RT T1
2009 Asia and South Pacific Design Automation Conference
: T1
CriAS: A performance-driven criticality-aware synthesis flow for on-chip multicycle communication architecture
UL https://suche.suub.uni-bremen.de/peid=ieee-4796443&Exemplar=1&LAN=DE A1 Chia-I Chen A1 Huang, Juinn-Dar YR 2009 SN 2153-6961 SN 2153-697X K1 Delay effects K1 Wire K1 Clocks K1 Delay estimation K1 Computer architecture K1 System performance K1 Simulated annealing K1 System-on-a-chip K1 Inductance K1 Frequency SP None LK http://dx.doi.org/https://doi.org/10.1109/ASPDAC.2009.4796443 DO https://doi.org/10.1109/ASPDAC.2009.4796443 SF ELIB - SuUB Bremen
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