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A 2 ns zero wait state, 32 kB semi-associative L1 cache:

, In: 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC,
Covino, J. ; Conner, J. ; Evans, D.... - p. 154-155, 435 , 1996
Link: https://doi.org/10.1109/ISSCC.1996.488550