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Process optimization for preventing boron-penetration using..:
, In:
1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers
,
Sun, W.T.
;
Chen, S.H.
;
Lin, C.J.
.. - p. 40,41,42,43 , 1995
Link:
https://doi.org/10.1109/VTSA.1995.524630
RT T1
1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers
: T1
Process optimization for preventing boron-penetration using P or As co-implant in P-poly gate of P-MOSFETs
UL https://suche.suub.uni-bremen.de/peid=ieee-524630&Exemplar=1&LAN=DE A1 Sun, W.T. A1 Chen, S.H. A1 Lin, C.J. A1 Chao, T.S. A1 Hsu, C.C.-H. YR 1995 SN 1524-766X K1 Annealing K1 Boron K1 Silicon K1 MOS capacitors K1 MOSFET circuits K1 Laboratories K1 Implants K1 Threshold voltage K1 Fabrication K1 Oxidation SP 40,41,42,43 LK http://dx.doi.org/https://doi.org/10.1109/VTSA.1995.524630 DO https://doi.org/10.1109/VTSA.1995.524630 SF ELIB - SuUB Bremen
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