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1 Ergebnisse
1
FPGA Based Implementation of High Performance Architectural..:
, In:
2009 International Conference on Advances in Recent Technologies in Communication and Computing
,
Joseph, Neenu
;
Sankarapandiammal, K.
;
Sabarinath, S.
- p. None , 2009
Link:
https://doi.org/10.1109/ARTCom.2009.230
RT T1
2009 International Conference on Advances in Recent Technologies in Communication and Computing
: T1
FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core
UL https://suche.suub.uni-bremen.de/peid=ieee-5328088&Exemplar=1&LAN=DE A1 Joseph, Neenu A1 Sankarapandiammal, K. A1 Sabarinath, S. YR 2009 K1 Field programmable gate arrays K1 Reduced instruction set computing K1 Process design K1 Fabrication K1 Energy consumption K1 Batteries K1 Pipeline processing K1 Decoding K1 Digital cameras K1 Printers K1 Architectural level power reduction K1 High speed architecture K1 Micro architecture K1 Common power format SP None LK http://dx.doi.org/https://doi.org/10.1109/ARTCom.2009.230 DO https://doi.org/10.1109/ARTCom.2009.230 SF ELIB - SuUB Bremen
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