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1 Ergebnisse
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VHDL simulation of peak detector, 64 bit BCD counter and re..:
, In:
2010 6th International Colloquium on Signal Processing & its Applications
,
Emilliano
;
Chakrabarty, Chandan Kumar
;
Ghani, Ahmad Basri A.
. - p. 1-7 , 2010
Link:
https://doi.org/10.1109/CSPA.2010.5545328
RT T1 <cTitle>2010 6th International Colloquium on Signal Processing & its Applications</cTitle>: T1 <Title>VHDL simulation of peak detector, 64 bit BCD counter and reset automatic block for PD detection system using FPGA</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-5545328&Exemplar=1&LAN=DE A1 Emilliano A1 Chakrabarty, Chandan Kumar A1 Ghani, Ahmad Basri A. A1 Ramasamy, Agileswari K. YR 2010 K1 Counting circuits K1 Field programmable gate arrays K1 Partial discharges K1 Radiation detectors K1 Signal processing K1 Acoustic signal detection K1 Signal synthesis K1 Signal detection K1 Probes K1 Latches K1 Partial Discharge Detection K1 FPGA Simulation K1 FPGA Technology K1 ADC with Peak Detector Block K1 Real Time Processing K1 Underground Cable K1 Counter with Reset Block K1 VHDL Programming SP 1 OP 7 LK http://dx.doi.org/https://doi.org/10.1109/CSPA.2010.5545328 DO https://doi.org/10.1109/CSPA.2010.5545328 SF ELIB - SuUB Bremen
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