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1 Ergebnisse
1
VHDL simulation of reset automatic block, 64 bit latch bloc..:
, In:
2010 IEEE Control and System Graduate Research Colloquium (ICSGRC 2010)
,
Emilliano
;
Chakrabarty, Chandan Kumar
;
Ghani, Ahmad Basri Abdul
. - p. 14-19 , 2010
Link:
https://doi.org/10.1109/ICSGRC.2010.5562530
RT T1 <cTitle>2010 IEEE Control and System Graduate Research Colloquium (ICSGRC 2010)</cTitle>: T1 <Title>VHDL simulation of reset automatic block, 64 bit latch block, and test complete blocks for PD detection circuit system using FPGA</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-5562530&Exemplar=1&LAN=DE A1 Emilliano A1 Chakrabarty, Chandan Kumar A1 Ghani, Ahmad Basri Abdul A1 Ramasamy, Agileswari K. YR 2010 K1 Radiation detectors K1 Latches K1 Partial discharges K1 Field programmable gate arrays K1 Programming K1 Simulation K1 Clocks K1 Partial Discharge Detection K1 FPGA Simulation K1 FPGA Technology K1 ADC with Peak Detector Block K1 Real Time Processing K1 Underground Cable K1 Counter with Reset Block K1 VHDL Programming SP 14 OP 19 LK http://dx.doi.org/https://doi.org/10.1109/ICSGRC.2010.5562530 DO https://doi.org/10.1109/ICSGRC.2010.5562530 SF ELIB - SuUB Bremen
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