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1 Ergebnisse
1
Low power circuits and microarchitectures for gigascale int..:
, In:
ASIC, 2003. Proceedings. 5th International Conference on
,
Yibin Ye, Yibin Ye
;
Jianping Xu, Jianping Xu
- p. None , 2003
Link:
https://doi.org/10.1109/ICASIC.2003.1277428
RT T1
ASIC, 2003. Proceedings. 5th International Conference on
: T1
Low power circuits and microarchitectures for gigascale integration
UL https://suche.suub.uni-bremen.de/peid=ieee-5733616&Exemplar=1&LAN=DE A1 Yibin Ye, Yibin Ye A1 Jianping Xu, Jianping Xu YR 2003 SN 1523-553X K1 circuit optimisation K1 integrated circuit design K1 leakage currents K1 low-power electronics K1 system-on-chip K1 10 Gbit/s K1 Ethernet K1 SOC K1 TCP-IP processor K1 active power reduction K1 design productivity K1 dynamic body bias technique K1 dynamic sleep transistor K1 functional blocks integration K1 gigascale integration K1 leakage problem K1 leakage reduction K1 low power circuits K1 microarchitectures K1 power delivery K1 power dissipation K1 power efficiency K1 subthreshold leakage K1 supply voltage scaling K1 system on a chip K1 technology scaling SP None LK http://dx.doi.org/https://doi.org/10.1109/ICASIC.2003.1277428 DO https://doi.org/10.1109/ICASIC.2003.1277428 SF ELIB - SuUB Bremen
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