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1 Ergebnisse
1
Design and implementation of a reconfigurable architecture ..:
, In:
ASIC, 2003. Proceedings. 5th International Conference on
,
Yang Yu, Yang Yu
;
Mao Zhigang, Mao Zhigang
;
Lai Fengchang, Lai Fengchang
.. - p. None , 2003
Link:
https://doi.org/10.1109/ICASIC.2003.1277572
RT T1
ASIC, 2003. Proceedings. 5th International Conference on
: T1
Design and implementation of a reconfigurable architecture for DSP
UL https://suche.suub.uni-bremen.de/peid=ieee-5733759&Exemplar=1&LAN=DE A1 Yang Yu, Yang Yu A1 Mao Zhigang, Mao Zhigang A1 Lai Fengchang, Lai Fengchang A1 Zhao Bin, Zhao Bin A1 Xia Yifei, Xia Yifei YR 2003 SN 1523-553X K1 FIR filters K1 fast Fourier transforms K1 parallel processing K1 pipeline processing K1 radar signal processing K1 radionavigation K1 reconfigurable architectures K1 DSP algorithms K1 FFT K1 FIR K1 RPE K1 ReDAr K1 automatic navigation equipment K1 crossbar interconnect network K1 data sequencing K1 digital signal processing algorithms K1 fast Fourier transform K1 finite impulse response K1 memory organization K1 parallel framework K1 pipelined framework K1 radar system K1 reconfigurable architecture K1 reconfigurable processing element K1 vector operations SP None LK http://dx.doi.org/https://doi.org/10.1109/ICASIC.2003.1277572 DO https://doi.org/10.1109/ICASIC.2003.1277572 SF ELIB - SuUB Bremen
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