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Simulation of logic/IDDQ tests for resistive shorts in logi..:
, In:
Digest of Papers IEEE International Workshop on IDDQ Testing
,
Hung-Jen Lin
;
Milor, L.
- p. 114,115,116,117 , 1997
Link:
https://doi.org/10.1109/IDDQ.1997.633024
RT T1
Digest of Papers IEEE International Workshop on IDDQ Testing
: T1
Simulation of logic/IDDQ tests for resistive shorts in logic circuits by using simplicial approximation
UL https://suche.suub.uni-bremen.de/peid=ieee-633024&Exemplar=1&LAN=DE A1 Hung-Jen Lin A1 Milor, L. YR 1997 K1 Logic circuits K1 Logic testing K1 Circuit testing K1 Circuit simulation K1 Circuit faults K1 Voltage K1 Computational modeling K1 Current supplies K1 Power supplies K1 Logic gates SP 114,115,116,117 LK http://dx.doi.org/https://doi.org/10.1109/IDDQ.1997.633024 DO https://doi.org/10.1109/IDDQ.1997.633024 SF ELIB - SuUB Bremen
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