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1 Ergebnisse
1
Radix-4 Max-log-MAP parallel turbo decoder architecture wit..:
, In:
2012 International Symposium on Intelligent Signal Processing and Communications Systems
,
Adiono, Trio
;
Marvin
- p. 792-797 , 2012
Link:
https://doi.org/10.1109/ISPACS.2012.6473599
RT T1
2012 International Symposium on Intelligent Signal Processing and Communications Systems
: T1
Radix-4 Max-log-MAP parallel turbo decoder architecture with a new cache memory data flow for LTE
UL https://suche.suub.uni-bremen.de/peid=ieee-6473599&Exemplar=1&LAN=DE A1 Adiono, Trio A1 Marvin YR 2012 K1 Decoding K1 Measurement K1 Cache memory K1 Signal processing algorithms K1 Computer architecture K1 Generators K1 Hazards K1 Turbo decoder K1 LTE K1 parallelization K1 Max-log-MAP radix-4 K1 data hazard K1 branch metric K1 cache memory SP 792 OP 797 LK http://dx.doi.org/https://doi.org/10.1109/ISPACS.2012.6473599 DO https://doi.org/10.1109/ISPACS.2012.6473599 SF ELIB - SuUB Bremen
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